Semiconductor memory devices have undergone various design changes in terms of package density, operating speed, or power/current dissipation. Many devices, such as micro-processors, or other related devices include onboard memory, which contains one or more SRAM cells for data storage. The SRAM cells are more popular than dynamic-random-access-memory (DRAM) cells, as the SRAM cells operate at a higher speed with indefinite data storage capabilities, unlike the DRAM cells, which must be periodically refreshed. The SRAM memory is vastly employed in various telecommunication devices and networking devices, in workstations and high performance PCs, in advanced modems and complex military/industrial applications.
The amount of read current provided by an SRAM cell is decreased when the size of the SRAM cell is decreased. In particular, the read current is decreased with a decrease in a supply voltage due to new advancements. In contrast, the relative magnitude of the leakage current increases with decreased read current. With an increased leakage current, the reading of data from the SRAM cell becomes more difficult. The increased sub-threshold leakage and gate leakage current not only increase the integrated circuit (IC) reliability issues, but also increase the package cost in order to handle the excess power dissipation. The Metal Oxide Semiconductor (MOS) transistors used in the SRAM cells can be subjected to dielectric damage and reliability problems due to an excessive voltage developed across the gate oxide.
Various conventional techniques, such as gated Vdd cache, diode footed cache, dual Vt cells, etc. have been employed for reducing the leakage currents. Most of the conventional techniques either change substrate-bias equations to change the threshold voltage of a transistor, or lower the effective supply voltage to the SRAM cell during the inactive mode. The conventional techniques involve large dynamic power dissipation, when the SRAM cell moves from an inactive state to an active state or vice-versa. Also, the conventional techniques save the leakage current only when the SRAM cell is in the inactive mode. Moreover, a conventional SRAM cell takes significant time to move from the inactive mode to the active mode or vice-versa, hence there is a huge penalty of time.
FIG. 1A illustrates a conventional 6-T SRAM cell for reducing leakage current. The interconnectivity of different NMOS and PMOS transistor is shown in the circuit diagram. The MOS transistor MP1, MN2, and MN3 dissipates significant sub-threshold leakage because of a drain induced barrier lowering effect (DIBL). The sub-threshold leakage through transistor MN2 is highest. The transistor MN2, MN4, and MN3 dissipates gate leakage due to edge tunneling, while the transistor MN1 dissipates gate leakage due to on direct tunneling, and hence the transistor MN1 dissipates maximum gate leakage. The gate leakage through any of the PMOS transistor is small due to their P-type nature (higher barrier height in a PMOS as compared to that in an NMOS transistor).
FIG. 1B illustrates a 7-T SRAM cell (100) for reducing leakage current. The 7-T SRAM cell (100) is an extension of a conventional 6-T SRAM cell (described in FIG. 1A) in which an extra transistor (106) is inserted to form the 7-T SRAM cell (100). The extra transistor (106) is operatively coupled to provide low leakage currents when a bit ‘0 is stored in the 7-T SRAM cell (100). The extra transistor (106) lowers the effective supply voltage to minimize the leakages in the cell. The SRAM cell (100) receives the input voltage signal Vdd, and is connected to a bit line (BL)/complementary bit line (/BL), and a word line (WL) for read, write or erase operations. A bit ‘0’ is stored at node A and bit ‘1’ is stored at node B. The gate voltage of the extra transistor (106) (shown as Vc) is kept at the input voltage signal Vdd. The extra transistor (106) will pass this gate voltage as Vdd-Vth to node C (Vth is the threshold voltage of the extra transistor 106). The node C is connected to the pass transistor (112). The gate voltage of the transistor (110) thus reduces to Vdd-Vth, which strongly suppress the gate leakage through the transistor (110). The reduced leakage currents are marked by dotted lines. The 7-T SRAM cell (100) reduces the leakage currents only when bit ‘0’ is stored in the cell. However, when bit ‘1’ is stored in the cell, there is no leakage benefit and the extra transistor (106) even dissipates some extra leakage current. The 7-T SRAM cell (100) exploits the fact that the SRAM cell stores ‘0’ for roughly 70% of the times and stores ‘1’ for the rest. Hence, a new SRAM cell is required, which can suppress leakages, when either bit ‘0’ or ‘1’ is stored in the SRAM cell.
There arises a need for an SRAM cell suitable for reducing leakage currents irrespective of the data stored in the SRAM cell. Moreover, the SRAM cell operates in active mode and thus there are no transition delays and dynamic power dissipation during transition (active mode to inactive-mode and vice-versa) operations as are there in most of the conventional techniques.